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agilent HDMP-2689 quad 2.125/1.0625 gbd fibre channel general purpose serdes data sheet description the HDMP-2689 serdes chip transmits and receives high speed serial data over fiber optic or coaxial cable interfaces that conform to ansi x3t11 fibre channel specification. it sup- ports serdes-only mode using a 10-bit data interface with op- tional 8b/10b encoding for fast backplane applications. the HDMP-2689 runs at 2.125 gbd or 1.0625 gbd data rates and provides parallel-to-serial and serial-to-parallel conversion on four independent channels contained in one package. an on- chip phase locked loop (pll) synthesizes the high speed transmit clock from a low speed (106.25 mhz) reference. each receivers on-chip pll synchro- nizes directly to the incoming data stream, providing clock and data recovery. both the transmit- ter and receiver support differen- tial i/o for fiber optic component interfaces, which minimizes crosstalk and maximizes signal integrity. chip control and status are accessed via the media independent interface (mii) defined in ieee 802.3. features ? 1.0625gbd and 2.125 gbd serial data rates ? tx and rx data rates independently selectable for each channel ? fibre channel (t11) compatible ? high speed differential serial i/o with matched 50 ? impedance ? supports fibre channel protocols fc0 ? dual mode serdes operation with 10-bit parallel data interface and optional 8b/10b encode/decode ? standard comma recognition for positive (0011111xxx) and negative (1100000xxx) disparity ? source-centered, double data rate clocking of receive parallel data for 1.0625 gbd and 2.125 gbd serial rates ? source synchronous double data rate clocking of transmit parallel data for 2.125 gbd serial rate ? source synchronous single data rate clocking of transmit parallel data for 1.0625 gbd serial rate ? mii management interface for chip control and status ? 1.8v core power supply, 2.5v power supply for sstl_2 i/o ? independent channel power-down for power savings ? sstl_2 compliant parallel i/o and byte clocks ? low transmit jitter ? pre-emphasis on serial outputs controllable via the management interface ? loss of signal detection ? ac-coupled differential lvpecl reference clock input ? input equalization ? boundary scan ieee 1149.1 compliant ? serdes self-test capability using prbs or user-defined patterns ? local internal loop back of tx serial data to rx serial data by channel ? 289-pin pbga ? testjet compliant
2 figure 1. HDMP-2689 typical applications. fiber optic interface (or copper) fast serial backplane fast backplane interface hfbr-5720l hfbr-5720l hfbr-5720l hfbr-5720l HDMP-2689 serial interface parallel interface parallel interface mac HDMP-2689 applications ? fibre channel arbitrated loop ? fast serial backplanes see figure 1 for a diagram of typical applications. functional description transmitter description the HDMP-2689 transmitter contains four independent channels and a single tx pll which generates the serial rate transmit clock for all of the channels. the data is optionally encoded in 8b/10b format and serialized at 1.0625 gbd (half rate) or 2.125 gbd (full rate). the high-speed outputs can be figure 2. tx and rx paths. interfaced directly to copper cables or pcb traces for electri- cal transmission or to a separate fiber optic module for optical transmission. see figure 2 for a block diagram. rxan rxap losa pmx rda[9:0] rca txan txap receive path tda[9:0] tca mdio transmit path pmx tdi, tdo, tms tclk, trstn mdc rfcp rfcn los cdr tx_fifo loopback data path serializer bit rate clock amplitude pre-emphasis control clock generator decode 8b/10b encode 8b/10b de-serializer loopback control input latch bit rate clock core clock core clock transmit pll core clock control mdio interface jtag port (ieee 1149.1) status notes: transmit/receive paths show only channel a, which is 1 of 4 channels. items in bold are external pins.
3 reference clock input the HDMP-2689 accepts a differential lvpecl reference clock input at 106.25 mhz (see figure 3 for configuration). this reference clock is used by the tx pll to acquire frequency lock and generate the base frequency of operation. 0.1 f 0.1 ? rfcp rfcn figure 3. reference clock input configuration. data input the transmitter is designed to accept either of two formats of parallel input data: ? 9-bit data consisting of an 8-bit word plus a 1-bit k character flag (z), encoded on chip with 8b/10b ? 10-bit data already encoded in a dc-balanced code (over a minimum length of 20 bits) such as 8b/10b the pmx pin is set to select the data format. depending on the format, the data may undergo encoding before serialization. see table 1 for pmx encoding defini- tions and data processing. table 2 contains a summary of the data formats. note that for the buffer mode (pmx=0), bit a, which corresponds to tdn9, is serialized first. for example, for k28.5 (0011111010), if the mac s out0 through out9 bits corre- spond to 0011111010, then the HDMP-2689 s tda9 through tda0 are connected to the mac s out0 through out 9. the tda9 bit is serialized first. similarly on the rx side, the very first bit received is rda9 (msb) which is in0 for the mac. see figure 4 for mac to HDMP-2689 connections. (channel a, shown in the figure, is representative of all four channels.) for codec mode, the mac s out0 through out9 should be con- nected to tda0 through tda9. for example, if 1bc=01 1011 1101 is coming from the mac for encoding, out0 (assuming this is the lsb from the mac) is 1, out1 is 0 and so on. after encoding, the result is a comma, 0011111010 (or 1100000101), with the leading 00 (or 11) bits coming first on the serial output. the rx side behaves in a similar fashion. the parallel input data arrives on sstl_2 inputs and is captured by data latches which are clocked by the local transmit clocks (tc[a-d]). the tx_fifo phase aligns the data with the internal core clock. 8b/10b encoding the HDMP-2689 provides a global 8b/10b line coding option. the characters defined by this code ensure a dc balanced serial data stream, which enables clock recovery at the receiver. the 8b/10b code distinguishes d-characters, used for data transmission, from k-characters, used for control or protocol functions. a byte error code can be designated as the replacement data for an erroneous data word by programming bits 14 through 6 of management interface register 19. half rate/full rate the HDMP-2689 supports two transmit data rates as detailed in table 3. the 10-bit wide parallel data is multiplexed into a 1.0625 gbd (half rate) or 2.125 gbd (full rate) serial data stream using internally gener- ated high-speed clocks. the data bits are transmitted sequentially from tdn[9] to tdn[0] (bit ordering for buffer and codec modes is shown in table 2). the output serial data rate is selected by programming bit 15 in man- agement interface register 17. figure 4. mac to HDMP-2689 interconnect. mac chip out9 out8 . . . out0 in9 in8 . . . in0 buffer mode hdmp- 2689 tda0 tda1 . . . tda9 rda0 rda1 . . . rda9 . . . . . . txa serial data out rxa serial data in out9 out8 . . . out0 in9 in8 . . . in0 codec mode hdmp- 2689 tda9(err) tda8(z) . . . tda0(d0) rda9(err) rda8(z) . . . rda0(d0) . . . . . . txa serial data out rxa serial data in mac chip
4 for half rate operation, the data is input in single data rate (sdr) mode. for sdr each parallel input data word is clocked in on the falling edge of the input transmit byte clock (tc[a-d]). the timing requirements are specified in figure 9 case a. for full rate operation, the data must be input in double data rate (ddr) mode, with one data word input on the rising edge of the input transmit byte clock (tc[a-d]) and the next word on the falling edge. two data words are input every transmit byte clock cycle. the timing require- ments for ddr operation are shown in figure 9 case b. tc[a-d] always operates at 106.25 mhz. the default settings for the HDMP-2689 are full rate opera- tion and ddr. serial data outputs through ac coupling, the high- speed outputs are capable of interfacing directly to copper cables or pcb traces for electri- cal transmission or to a separate fiber optic module for optical transmission (see figure 5). these outputs include user- controllable skin-loss equaliza- tion and amplitude control to improve performance when driving copper lines. in normal operation, the serialized tdn[9:0] data is placed at txnp/n. the output drivers provide for controllable pre- emphasis and amplitude settings by programming management interface register 26 (see fig- ure 6). if pre-emphasis is used, 0 1 and 1 0 transitions on txnp/n have greater amplitude than 0 0 and 1 1 transitions. this increased amplitude coun- teracts the effects of skin loss and dispersion on long pcb transmission lines. the serial outputs can also be disabled through register 26. 0.01 f 0.01 f z 0 =50 ? z 0 =50 ? to core of chip 100 ? gnda esd protection vdda hs_in rxnp rxnn gnda vdda from core of chip 50 ? txnp 50 ? gnda esd protection vdda hs_out txnn gnda vdda notes: hs_in inputs should never be connected to ground as permanent damage to the device may result. capacitors may be placed at the sendin g or receivin g end. note: the peaked value at the transition edge does not reach to v peak_static value because of the reflection between driver and package. the static value can be measured as the final value of a long (longer than 2 bits) 1 or 0 pulse with zero peaking. v diff =v txp -v txn v peak_static v peak peak[2:0]=7 peak[2:0]=0 v sustain peaking levels figure 5. high speed input and output configurations. figure 6. high speed output pre-emphasis.
5 receiver description the HDMP-2689 receiver con- tains four independent channels, each with its own input amplifier with equalization, clock recovery pll, deserializer, comma detec- tion and byte clock generation. depending on the pmx mode, the data may also pass through an 8b/10b decoder. high speed input in normal operation, serial data is accepted at rxnp/n and converted into parallel data to drive rdn[9:0]. see figure 5 for the input configuration. in parallel loopback mode, the internal serial output signal from the transmitter section is used to generate rdn[9:0]. loopback is discussed in more detail in the section on test. receiver loss of signal when the peak-to-peak differen- tial amplitude at the rxnp/n input is too small, losn is set to logic 1. when the signal at rxnp/ n is a valid amplitude, losn is set to logic 0. if rxnp/n 300 mv peak-to- peak differential, losn = logic 0 if 150 mv < rxnp/n < 300 mv peak-to-peak differential, losn is undefined if rxnp/n 150 mv peak-to- peak differential, losn = logic 1 optionally, through mii register 17, losn can also be forced to logic 1 if the receiver pll is not locked. rx pll/clock recovery the receiver frequency and phase locks onto the incoming serial data stream and recovers the bit clock. the rx pll locks onto the input data by frequency locking onto the 106.25 mhz lvpecl reference clock and then phase locking onto the selected input data stream. the received clock locks to the incoming data or free runs at the selected frequency in the absence of incoming data. an internal signal detection circuit monitors the presence of the input and in- vokes phase detection as the data stream appears. once bit locked, the receiver generates the high- speed sampling clock used to deserialize the data. byte sync and comma detect as the 10-bit parallel data is recovered from the high-speed serial bit stream, the first seven bits of the k28.5+ positive disparity comma character (0011111xxx) and of the k28.5- negative disparity comma charac- ter (1100000xxx) are detected. the proper parallel data edge is selected out of the bit stream so that the next comma character starts at rdn[9] in buffer mode. when a comma character is detected and realignment of the receive byte clock is necessary, the clocks are stretched (never slivered) to the next correct alignment position. the recov- ered clock will be aligned by the start of the next four-byte ordered set after k28.5+ or k28.5- is detected. by default, in buffer mode, the start of the next ordered set will be aligned with the falling edge of rcn. in codec mode (pmx=1), by default the rcn clock is not realigned, and the comma may appear at either edge. the default alignments may be changed by programming mii register 17. unless comma edge alignment is disabled in mii register 17, comma characters must not be transmitted in consecutive bytes so that the receive byte clocks may maintain their proper recovered frequen- cies. furthermore, rx byte align should be disabled (using mii register 24) if prbs data is being received. sstl_2 outputs as discussed for the transmitter parallel inputs, the bit ordering is different for buffer and codec modes. see figure 4 and earlier data input section for additional details. the HDMP-2689 presents the 10-bit parallel recovered data (rdn[9:0]), properly aligned to the receive byte clock (rcn) as shown in figure 11 and table 5, as single-ended sstl_2 compli- ant signals. the HDMP-2689 expects sstl_2 compatible signals at the tdn[9:0] and tcn pins. see figure 7 for a simplified schematic of the input and output drivers, and figure 8 for the recommended termination configuration. for proper opera- tion of the terminated sstl_2 drivers, register 23 must be configured as described in management interface registers, page 2 7 . (set regis t er 23 to 0x1218). for best results use a low inductance vterm plane to terminate the 50 ? resistors close to the HDMP-2689 tx inputs. in addition, decouple the vterm plane with 0.1 f local to each 10-bit channel to reduce simultaneously switching output (sso) noise on the inputs. the HDMP-2689 works with mac devices whose vddq voltage is nominally 2.5 v. in addition, the HDMP-2689 provides a vref output pin which may be used at the protocol ic in order to differentially detect a high or a low on rdn[9:0]. alternatively, this voltage may be generated on the pcb using a resistor divider from vddq while ignoring the vref output of the HDMP-2689.
6 figure 7. simplified schematic of sstl_2 input and output drivers. figure 8. sstl_2 i/o terminations. vddq vddq pad pad from core of chip gnd gnd digital output 50 ? nominal output impedance esd protection esd protection to core of chip digital input i/o 50 ? vterm (vddq/2) a) terminated sstl_2 connection, rx 0.1 f controller HDMP-2689 data in vrefi z 0 = 50 ? vref data out 50 ? vterm (vddq/2) b) terminated sstl_2 connection, tx z 0 = 50 ? controller HDMP-2689 data in data out data output and clocking modes table 5 describes the receive parallel interface clocking. in both half (1.0625 gbd serial ) and full (2.125 gbd serial) rate operation, the data is always presented as ddr, double data rate (see figure 11, cases a and b). in addition, the output clock is always source centered (sc), so the clock changes in the middle of the data period. note that bit a, the first serial bit in a 10-bit word, corresponds to rdn9 (see table 2). configuration and reset the HDMP-2689 is configured by a set of registers that can be accessed through the standard mii management interface defined in ieee 802.3 clause 22. this interface is used by a management entity to control and gather status from the chip. it is a two-wire interface made up of a management data input/ output signal (mdio) and a management data clock (mdc). figure 15 shows the relationship between mdio and mdc. figure 16 and figure 17 present a more detailed description of mdio timing. table 8 presents the format of a management frame (for more information, refer to ieee 802.3). a management frame consists of a minimum 32-bit preamble, a start of frame indication, an operation code, a phy address, a register address, turnaround bits, data bits, and an idle. the order of bit transmis- sion is left to right as shown in table 8. mdio timing is detailed in table 9. the three most significant bits of the phy address are made up of the hard-wired address of the HDMP-2689. the two least signifi- cant bits represent the channel referenced in the frame. two bits are sufficient to encode ids for the four channels on the chip. the standard management interface allows for 32 16-bit registers. the HDMP-2689 sup- ports a subset of these registers. management interface registers, pages 26?8 , sh o w t he s t anda r d register definitions and specify which ones are supported in the HDMP-2689. because the HDMP-2689 has four physical channels that operate indepen- dently, some of the registers are replicated four times, one for each channel. other registers are common to all four channels, i.e. their bit values apply to all the channels. still other registers are shared between the four channels, i.e. individual bits within a register apply to individual channels. the replicated registers are accessed using a phy address made up of the three-bit chip id and the appropriate two-bit channel id (00, 01, 10, or 11). common and shared registers are accessed using the chip id and the 00 channel id. attempting to access common registers other than through channel a (00) must be avoided as it results in unde- fined behavior. the specific configuration and status informa- tion that can be set or read from HDMP-2689 is presented in the section titled management interface registers. this section defines the complete assignment of management registers and specifies which registers are common to the four channels.
7 reset is initiated externally with the assertion of the rstn pin. before asserting the rstn pin, the power supply to the chip and the reference clock (rfcp/n) must be stable for at least 20 s. the rstn pin must be held low for at least 100 ns. after reset is de-asserted, 500 s must elapse before initiat- ing mdio transactions (see figure 13). note that the transmit byte clocks (tcn) should be running and stable when reset is released to minimize the variation in transmit latency. power management the HDMP-2689 incorporates the ability to power down any channel which is unused. both the channel and the associated output driver should be disabled by programming the unused channel s register 24, bit 0 and register 26, bit 7 both to logic 0. additionally, the HDMP-2689 does not require a particular power turn-on sequence. power supply decoupling recommended power supply filtering and placement of decoupling capacitors for the HDMP-2689 are shown in figure 22 and figure 23. test the HDMP-2689 has several features to facilitate testing, including boundary scan, serdes self-test, and loopback for link debugging. boundary scan is implemented according to the ieee 1149.1 standard. the instructions listed in table 7 are supported. the HDMP-2689 also provides self-test capabilities with user-entered patterns or on- chip generation of pseudo- random bit streams (prbs 2 7 C 1). the patterns can be looped back either internally or externally from the transmit serializer to the receive deserializer and are verified within the chip. these self-test mechanisms are initi- ated and the error status re- ported through the mii manage- ment interface. to run a self-test, first select the pattern or set of patterns, then configure the loopback and check the results. once enabled, the test pattern is sent continuously. to select a user-defined pattern: ? disable comma alignment by programming bit 1 of register 24 to logic 0. ? program the pattern (any pattern except all 0 s or all 1 s) into bits 9 through 0 of register 25. ? to alternate the user pattern with its inverse, program bit 11 of register 25 to logic 1. ? program bit 10 of register 25 to a logic 1 to enable the user register pattern to be sent. to select prbs data: ? disable comma alignment by programming bit 1 of register 24 to logic 0. ? program a non-zero seed for the pattern generator into bits 9 through 0 of register 25. ? to send the prbs pattern inverted, program bit 11 of register 25 to logic 1. ? program bit 12 of register 25 to a logic one to enable the prbs pattern to be sent. ? to see the recovered prbs data on the parallel interface, comma edge alignment should be disabled by programming bit 13 of register 17 to logic 0. to run the self-test with either external or internal loopback: ? set up either a user-defined pattern or prbs data as outlined above. ? to run with internal loopback, program bit 13 of register 25 to logic 1. ? to run with external loopback, connect the high-speed output of the channel being tested (txap/n, txbp/n, txcp/n, txdp/n) back to its high speed input (rxap/n, rxbp/n, rxcp/n, rxdp/n). bit 13 of register 25 must be logic 0 (default value after reset). ? program bit 14 of register 25 to logic 0 if it is not already zero (default value after a reset). bit 12 of register 27 (pattern failure detect) and bit 11 of register 27 (test run complete) should both now be logic 0. ? program bit 14 of register 25 (pattern error monitor enable) to logic 1. this starts the pattern checking process. for a prbs pattern 2 9 bytes are checked before the test is considered complete. ? monitor bit 11 of register 27 to determine if a sufficient number of cycles have elapsed for test completion. when this bit is logic 1, bit 12 of register 27 signals pass (logic 0) or fail (logic 1). to allow link debugging: ? configure the HDMP-2689 for internal loopback (data pro- vided at the parallel input is looped back to the parallel output after traversing the chip) via management interface register 25 bit 13. note that for internal loopback in codec mode the receiver sees a loss of signal and error bit 9 (see table 2) is set, unless the high speed inputs (ignored for internal loopback) are being driven.
8 table 1. pmx encoding definitions. pmx mode description 0 buffer tx: inputs are phase adjusted to transmit clock and serialized msb (a) first. rx: serial data is byte aligned and presented with first bit (a) as msb 1 codec tx: inputs are phase adjusted, 8b/10b encoded, and serialized. rx: serial data is byte aligned and 8b/10b decoded table 2. data formats (tda/rda is representative of all transmit and receive data ports). pin pmx 0 pmx 1 buffer codec tda9/rda9 a err (rx_los or decoding error) tda8/rda8 b z tda7/rda7 c d7 tda6/rda6 d d6 tda5/rda5 e d5 tda4/rda4 i d4 tda3/rda3 f d3 tda2/rda2 g d2 tda1/rda1 h d1 tda0/rda0 j d0 note: see figure 4 for a connection diagram. table 3. transmitter data rate. management register 17 txnp/n tcn input setting rate (gbd) rate (mhz) case full/half a 0 1.0625 106.25 b 1 2.125 106.25
9 table 4. HDMP-2689 transmitter section timing characteristics, t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max 1g tx cds [1,2] clock to data skew time; the data must be stable by t cds after the clock edge to ps 300 guarantee correct clocking of the data tx h [2] hold time; the time after the clock edge until which the data must remain stable ps 2000 to guarantee correct clocking of the data t_txlat_buffer [3] transmitter latency; the time between the latching edge of the transmit byte clock ns 80 tcn and the leading edge of the first transmitted serial output bit in buffer mode bits 85 t_txlat_codec [3] transmitter latency; the time between the leading edge of the transmit byte clock ns 90 tcn and the leading edge of the first transmitted serial output bit in codec mode bits 95.5 2g tx cds [1,2] clock to data skew time; the data must be stable by t cds after the clock edge to ps 300 guarantee correct clocking of the data tx h [2] hold time; the time after the clock edge until which the data must remain stable to ps 2000 guarantee correct clocking of the data t_txlat_buffer [3] transmitter latency; the time between the latching edge of the transmit byte clock ns 65 tcn and the leading edge of the first transmitted serial output bit in buffer mode bits 138 t_txlat_codec [3] transmitter latency; the time between the leading edge of the transmit byte clock ns 70 tcn and the leading edge of the first transmitted serial output bit in codec mode bits 149 notes: 1. this clock-to-data skew time is equivalent to ?00ps setup time. 2. measurement conditions were v ih = v ddq , v il = gnd. 3. due to the fifo which aligns the phase of the internal chip clock with the transmit byte clock (tcn) and the asynchronous nat ure of the chip reset, the typical latency varies; a maximum of the typical range is given. figure 9. transmitter timing diagram. 9.4 ns tcn tdn[9:0] tx h tx cdh case a. tx half rate sdr timing 9.4 ns tcn tdn[9:0] tx h tx cdh case b. tx full rate ddr timing tx cdh tx h test conditions: v ih = v ddq , v il = gnd
10 figure 10. transmitter latency. txp/n 10-bit char a 10-bit char b td[0] td[0:9] tc 10-bit char c txlat 10-bit char b figure 11. receiver timing diagram. 18.8 ns rcn rdn[9:0] case a. rx half rate ddr timing rx s rx h rx s rx h test conditions: v ih = v ddq , v il = gnd 9.4 ns rcn rdn[9:0] case b. rx full rate ddr timing rx s rx h rx s rx h table 5. receiver data rate. management register 17 rxnp/n rcn input setting rate (gbd) rate (mhz) case full/half a 0 1.0625 53.125 b 1 2.125 106.25
11 HDMP-2689 receiver section timing characteristics, t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max pwreset width of reset pulse ns 100 f lockrx the time that the rx pll takes to frequency lock to the data after reset s 500 b_sync_lock bit sync time after f lockrx bits 2500 b_sync_rate bit sync time after rate switch s 100 1g rx s [1] setup time: the time before the clock edge that the data will be stable ps 2700 rx h [1] hold time; the time after the clock edge until which the data will remain stable ps 1500 t_rxlat_buffer receiver latency; the timing between the leading edge of the first received serial ns 50 bit of a parallel data word and the leading edge of the corresponding parallel output bits 53 word in buffer mode t_rxlat_codec receiver latency; the timing between the leading edge of the first received serial ns 60 bit of a parallel data word and the leading edge of the corresponding parallel output bits 64 word in codec mode 2g rx s [1] setup time: the time before the clock edge that the data will be stable ps 1200 rx h [1] hold time; the time after the clock edge until which the data will remain stable ps 1400 t_rxlat_buffer receiver latency; the timing between the leading edge of the first received serial ns 30 bit of a parallel data word and the leading edge of the corresponding parallel output bits 64 word in buffer mode t_rxlat_codec receiver latency; the timing between the leading edge of the first received serial ns 35 bit of a parallel data word and the leading edge of the corresponding parallel output bits 75 word in codec mode notes: 1. tested under load conditions described in figure 12, with v ih = v ref + 0.18 and v il = v ref 0.18. sstl_2 output driver z 0 = 50 ? delay = 1.0 - 2.0ns c load = 4 pf 50 ? vterm (vddq/2) note: register 23 set to 0x1218. power supplies and rfcn/ rfcp have stabilized rstn 20 s 100 ns pw reset 500 s f lockrx program mdio figure 12. sstl_2 output test conditions. figure 13. externally applied reset (not to scale).
12 table 7. ieee jtag 1149.1 instructions. instruction opcode description extest 00000_00000 causes boundary jtag registers to capture their inputs, shift, and output to pads. sample 00000_00010 causes boundary jtag registers to capture their inputs. clamp 00000_00100 causes boundary jtag registers to output their values to pads. highz 00000_01000 causes pads to be tri-stated. bypass 11111_11111 connects the bypass register between tdi and tdo. table 8. format of a management frame. pr st op phyadd regadd ta data idle read 11...1 01 10 aaaaa rrrrr z0 dddddddddddddddd z write 11...1 01 01 aaaaa rrrrr 10 dddddddddddddddd z figure 15. mdio and mdc timing. mdc mdio table 9. mdio timing characteristics, t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max driving t delay mdc rising edge to mdio data true or mdio released ns 0 300 t mdc mdc frequency mhz 2.5 receiving t su set up time: mdio to mdc rising edge ns 10 t h hold time: mdc rising edge to mdio changing ns 10 note: for more information, see the ieee 802.3 part 3 22.3.4, mdio timing relationship to mdc. figure 14. receiver latency. rxp/n 10-bit char b 10-bit char c rd[0] rd[9] rd[0:9] rc 10-bit char a rxlat 10-bit char b
13 figure 16. mdio timing, driving and receiving. mdc mdio t delay mdc mdio t h t su figure 17. mdio timing diagrams. mdc mdio a a b c d station drives isb (least significant bit) of regular address on the mdio line station releases the mdio line unit (HDMP-2689) drives a low on the mdio line unit (HDMP-2689) drives bit 15 of the read register data note: all mdio changes are triggered from the rising edge of mdc. b c d mdc mdio a a b unit (HDMP-2689) drives isb (least significant bit) of read register data unit (HDMP-2689) releases the mdio line note: for more information, see the ieee 802.3 part 3 22.2.4.5. "management frame structure." b mdio timing, turn around (ta) cycles during a read. mdio timin g , last bit of read re g ister data, bus released b y the HDMP-2689.
14 table 10. HDMP-2689 absolute maximum ratings. sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. symbol parameters units min max v ddq i/o supply voltage v -0.5 4.0 v dd supply voltage digital core v -0.5 3.0 v dda analog supply voltage v -0.5 3.0 t stg storage temperature (not biased) c -55 125 t c case temperature, measured at top center of the package c0 95 t j junction temperature c 0 110 v inhs high speed input voltage (single-ended) v -0.5 v dda + 0.6 v inlvpecl lvpecl input voltage (reference clock rfcp/n) (single-ended) v -0.5 v dda + 0.6 v insstl sstl_2 input voltage v -0.5 v ddq + 0.8 esd electrostatic discharge, class 1 v -1000 1000 table 11. recommended operating conditions. symbol parameters units min typ max v ddq i/o supply voltage v 2.3 2.5 2.7 v dd supply voltage digital core v 1.7 1.8 1.9 v dda analog supply voltage v 1.7 1.8 1.9 t c case temperature, measured at top center of the package 0 c 0 25 85 table 12. guaranteed operating rates. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v parallel clock rate (mhz) serial baud rate (gbd) serial baud rate (gbd) min max min max min max 106.2 106.3 1.062 1.063 2.124 2.126 table 13. clock specifications. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max f reference clock nominal frequency (rfcp/n) mhz 106.25 symm[rfcp, rfcn] reference clock duty cycle % 40 60 f tol_full recovered clock (rcn) to reference clock rfcp/n frequency tolerance ppm -100 100 f tol_half recovered clock (rcn) to half the reference clock rfcp/n frequency tolerance ppm -100 100 symm[rcn] recovered clock duty cycle % 40 60 f tcn transmit byte clock nominal frequency mhz 106.25 symm[tcn] transmit byte clock duty cycle % 40 60 note: transmit clock and reference clock must be from the same frequency source.
15 table 14. HDMP-2689 power dissipation. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max i vdda [1] v dda current supply ma 500 590 i vddq [1] v ddq current supply ma 210 335 i vdd [1] v dd current supply ma 175 230 p d serdes total power dissipation w 1.7 2.5 note: 1. measurement conditions: full rate and half rate, random data. maximum value covers both terminated and unterminated condition s. table 15. sstl_2 i/o operating conditions. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max v ddq [1] supply voltage used to derive the sstl_2 input reference voltage v 2.3 2.5 2.7 v ih (dc) input high voltage v v ref + 0.18 v ddq + 0.3 v il(dc) input low voltage v - 0.3 v ref 0.18 v ih (ac) input high voltage v v ref + 0.35 v ddq + 0.3 v il(ac) input low voltage v - 0.3 v ref 0.35 v ref sstl_2 output reference voltage v 1.15 1.25 1.35 v term termination voltage v v ref - 0.04 v ref v ref + 0.04 v oh [2] output high voltage v v term + 0.38 v ol [2] output low voltage v v term 0.38 notes: 1. v ddq is the mac device i/o supply voltage. 2. see figure 12 for measurement conditions. table 16. HDMP-2689 cmos i/o operating conditions. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v, vddq is the fc-1mac device i/o supply voltage. symbol parameters units min typ max v ih input high voltage v 0.7 x v ddq v ddq v il input low voltage v gnd 0.3 x v ddq v oh output high voltage v v ddq 0.1 v ol output low voltage v gnd 0.4
16 table 17. HDMP-2689 ac electrical specifications. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max t r, rfcp/n rfcp/n lvpecl input rise time, v il, lvpecl to v ih, lvpecl ns 1.5 t f,rfcp/n rfcp/n lvpecl input fall time, v ih, lvpecl to v il, lvpecl ns 1.5 t rd, hs_out [1, 5] hs_out differential rise time, 20% to 80% ps 150 t fd, hs_out [1, 5] hs_out differential fall time, 80% to 20% ps 150 t r,sstl [2,3] sstl output rise time, v ol, sstl to v oh, sstl ns 2.3 t f,sstl [2,3] sstl output fall time, v oh, sstl to v ol, sstl ns 1.5 v ip,hs_in [4] hs_in input pk-pk differential voltage v 0.3 1.6 v pk,hs_out [1, 5] hs_out output pk-pk differential voltage, (z 0 = 50 ? ) [1] v 725 880 1050 v sustain,hs_out [1. 5] hs_out output sustain level differential voltage, (z 0 = 50 ? ) [1] v 675 830 1000 v ip, lvpecl rfcp, rfcn input swing (single ended) v 200 v dda notes: 1. measured with 2 pf capacitive load. 2. see figure 12 for test conditions. 3. sstl_2 ac input signals meet jedec standard no. jesd8-9a test conditions (minimum slew rate 1.0v/ns). see jedec table 3. 4. note los pin description. 5. measured at default settings, maximum amplitude and medium peaking (11111011). table 18. HDMP-2689 transmitter section output jitter characteristics. t c = 0 c to t c = 85 c, v ddq = 2.3 to 2.7 v, v dd = 1.7 to 1.9 v, v dda = 1.7 to 1.9 v symbol parameters units min typ max rj [1] random jitter at txnp/n (1s deviation of 50% crossing point) ps 4 dj [2] deterministic jitter at txnp/n (peak to peak), k28.5 +/k28.5- pattern ps 10 dj [3] deterministic jitter at txnp/n (peak to peak), crpat pattern ps 15 tj total jitter (tj=dj+14 * rj) (k28.5 +/k28.5- pattern) ps 66 j jitter tolerance fibre channel compliant notes: 1. defined by fibre channel specifications x3.230 1994 fc-ph, annex a section a4.4 (oscilloscope method) and tested using setup shown in figure 20. 2. defined by fibre channel specifications x3.230 1994 fc-ph, annex a section a4.4 and tested using the set up shown in figure 20. 3. defined by fibre channel technical report methodologies for jitter specifications, annex b, and tested using the set up shown in figure 20.
17 figure 18. serial output eye diagram. figure 19. serial output random jitter with tx pre-emphasis off.
18 a) block diagram of rj measurement method b) block diagram of dj measurement method 2.125 ghz 106.25 mhz *pattern generator provides pattern- synchronous trigger 70311a clock source static k28.7 from pattern generator or user pattern controlled by mdio HDMP-2689 rfcn rfcp txnp txnn tdn[9:0] 100 ? 0.1 f 0.1 f balun balun ch1 ch2 83480a oscilloscope trigger HDMP-2689 rfcn rfcp txnp txnn rdn[9:0] rxnp rxnn 2.125 ghz 70311a clock source -data 70841b pattern generator* +k28.5, -k28.5 or crpat +data 106.25 mhz tdn[9:0] divide by 20 trigger out 70841b pattern generator* 0011111100 static k28.7 divide by 20 83480a oscilloscope ch1 ch2 trigger 100 ? 0.1 f 0.1 f clock in figure 20. transmitter dj and rj measurement method. table 19 . pin input capacitance. symbol parameters units min typ max cinput input capacitance on sstl input pins pf 1.1 package information package thermal characteristics symbol parameter units typ max p dmax power dissipation w 2.5 ja [1] thermal resistance: junction to ambient air flow (lfpm) 0 c/w 27.8 200 c/w 24.3 400 c/w 23.1 600 c/w 22.1 jt [2] thermal characterization parameter: junction to package top c/w 4.8 jb [3] thermal characterization parameter: junction to board c/w 19.3 notes: based on independent package testing done by agilent, 1. ja is based on thermal measurement in still air environment at 25 c on a standard 4 x 4 fr4 pcb as specified in eia/jesd 51-9. 2. jt is used to determine the actual junction temperature in a given application, using the following equation: t j = jt x p d + t t where t t is the measured temperature on top center of the package (also known as case temperature, tc) and p d is the power being dissipated. 3. jb is used to determine the actual junction temperature in a given application, using the following equation: t j = jb x p d + t b where t b is measured board temperature, along the side of package at center on board surface and p d is the power being dissipated.
19 17.70 19.00 side view bottom view 289 solder balls top view 4 no. layers standard notes 1.76 0 .21 dim "a" 0.56 0 .06 dim "b" pbga thickness schedule 14.80 max. 3.55 7.30 17.70 +0.35 ?0.05 19.00 b 7.30 a1 ball pad corner 7. a1 ball pad indicator, 1.0 dia. optional area available marking 4 x 45 chamfer +0.35 ?0.05 3.55 14.80 max a 0.20 (4x) 0.35 c c c 0.25 5. 0.50 0.10 0.30 m cab c 0.10 m 6. c dim "b" dim "a" seating plane 0.80 0.05 0.40 0.10 0.15 30 typ a1 ball pad corner 1.50 ref 1.50 ref 2 4 6 8 10 12 14 16 1.00 0.50 r, 3 places 31 a b c d e f g h j k l m n p r t u 5 7 9 11 13 15 17 1.00 pin 1 corner agilent HDMP-2689 lllllllll-nn g yyww b2.3 aaaaaaaaaaa notes: unless otherwise specified 1. all dimensions and tolerances conform to asme y14.5m-1994. 2. the basic solder ball grid pitch is 1.00 mm. 3. solder ball matrix size is 17 x 17. 4. number of solder balls is 289. 5. dimension is measured at the maximum solder ball diameter. parallel to primary datum c. 6. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 7. a1 ball pad corner i.d. for plate mold: marked by laser. auto mold: dimple formed by mold cap. 8. this drawing conforms to the jedec registered outline ms-034/a. marking diagram: text code description lllllllll nn lllllllll=wafer lot number nn=wafer number b2.3 die revision g yyww g=supplier code date code (yy=year, ww=week) aaaaaaaaaaa country of assembly figure 21. package layout and marking top view.
20 0.01 f 0.01 f 0.1 f 0.1 f 0.01 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f + 10 f 0.1 f vdda _1 .8 v vdda _1 .8 v 0.1 f 0.1 f 0.01 f 0.1 f 0.1 f vddq_ 2 .5 v 0.01 f 0.1 f 0.1 f 0.1 f + 10 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 0.1 f vdd_ 1 .8 v + 10 f + 10 f (1 a/3 0 ohms / 1oo mhz (1a/30 ohms /100 mhz) + 10 f vdda 1 b2 vdda 1 c1 vdda 1 c3 vdda 1 d4 vdda 1 e7 vdda 3 b16 vdda 3 e11 vdda2 a4 vdda2 a8 vdda2 a10 vdda2 b6 vdda2 a14 vdda2 b12 vdda2 c5 vdda2 c7 vdda2 c11 vdda2 c13 vddq 15 vddq 11 vddq 7 vddq 3 vddq r17 vddq r13 vddq r1 vddq r5 vddq r9 vdd e4 vdd g1 3 vdd j5 vdd j13 vdd l5 vdd g5 vdda 3 c15 vdda 3 c17 vdda 3 d1 4 vdda2 d6 vdda2 d12 vdda2 e9 vddq n15 vddq n3 vddq l17 vddq l1 vddq j15 vddq j3 vddq g17 vddq e3 vddq g1 vdd n1 1 vdd n9 vdd n7 vdd m11 vdd m9 vdd m7 vdd l13 vdda 1 /3 0.01 f 0.01 f vdd_ 1 .8 v vdda 2 vdda 1 /3 HDMP-2689 guidelines for decoupling capacitor placements/connections figure 22. guidelines for decoupling capacitor connections. figure 23. recommended decoupling capacitor placement.
21 pin diagram transceiver pinout (top view) (rev 1.0) 19mm x 19mm body, 17mm by 17mm array, 289 pins populated, 1mm ball pitch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a rxap gnda rxbp vdda2 txap gnda txbp vdda2 rfcp vdda2 txcp gnda txdp vdda2 rxcp gnda rxdp a b rxan vdda1 rxbn gnda txan vdda2 txbn gnda rfcn gnda txcn vdda2 txdn gnda rxcn vdda3 rxdn b c vdda1 gnda vdda1 gnda vdda2 gnda vdda2 n/c gnda n/c vdda2 gnda vdda2 gnda vdda3 gnda vdda3 c d gndin rsvn1 gnda vdda1 gnda vdda2 gnda gnda gnda rrefa gnda vdda2 gnda vdda3 gnda gnd pmx d e gndd rsvn2 vddq vdd gnda gnda vdda1 gnda vdda2 gnda vdda3 gnda gnda gndin n/c n/c gndd e f tclk tms tdo tdi rstn gnda gnda gnda gnda gnda gnda gnda vref gnd dvad2 dvad1 dvad0 f g vddq losa gndd trstn vdd gnd gnd gnd gnd gnd gnd gnd vdd mdio mdc losd vddq g h rda9 rda8 rda7 rda6 gnd gnd gnd gnd gnd gnd gnd gnd gndin rcd rdd7 rdd8 rdd9 h j gndd rda5 vddq rca vdd gnd gnd gnd gnd gnd gnd gnd vdd rdd3 vddq rdd6 gndd j k rda4 rda3 rda0 tda7 gnd gnd gnd gnd gnd gnd gnd gnd gnd tdd7 rdd0 rdd4 rdd5 k l vddq rda1 gndd tda4 vdd gnd gnd gnd gnd gnd gnd gnd vdd tdd4 gndd rdd1 vddq l m rda2 tda8 tca tda2 losb gndin vdd gnd vdd gnd vdd gndin losc tdd2 tcd tdd8 rdd2 m n gndd tda6 vddq rdb9 gndd rdb4 vdd gndin vdd gndin vdd rcc gndd rdc9 vddq tdd6 gndd n p tda9 tda3 tda0 rdb7 rdb5 rdb1 tdb8 tdb4 tdb0 tcc tdc9 rdc2 rdc6 rdc7 tdd0 tdd3 tdd9 p r vddq tda1 gndd rdb3 vddq tdb9 gndd tdb3 vddq tdc4 gndd rdc0 vddq rdc5 gndd tdd1 vddq r t tda5 rdb8 rcb rdb2 tdb7 tdb6 tcb tdb2 tdc0 tdc3 tdc5 tdc6 tdc8 rdc3 rdc4 rdc8 tdd5 t u gndd rdb6 vddq rdb0 gndd tdb5 vddq tdb1 gndd tdc1 vddq tdc2 gndd tdc7 vddq rdc1 gndd u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 notes: gnd, gndin, and gndd may be connected together. gnda is recommended to be on a separate plane. i/o type definitions i/o type definition i-cmos cmos input i/o-cmos cmos bi-directional o-cmos cmos output i-lvpecl lvpecl input o-sstl2 sstl_2 output i-sstl2 sstl_2 input hs_in high speed input hs_out high speed output i-anlg analog input o-anlg analog output o-pvt pvt output s power supply or ground n/c no connection, must be floating
22 pin list i/o definition name pin type signal rstn f05 i-cmos chip reset (fifo clear): active low dvad0 f17 i-cmos device address input: 3 bit input address with dvad2 as msb. full address is the device address followed by the 2 bit dvad1 f16 channel address. dvad2 f15 pmx d17 i-cmos enable codec or buffer mode (see table 1) n/c c08, c10, n/c no connect: must be left floating. e15, e16 mdio g14 i/o-cmos mdio input/output: used to read/write the mdio registers. mdc g15 i-cmos mdio clock: input clock to the mdio control block. rfcp a09 i-lvpecl differential reference input clock: rfcp (+) and rfcn (-) is the106.25 mhz differential clock pins supplied to t he ic. rfcn b09 the clock ismultiplied up to generate the serial bit clock and other internal clocks. this is a lvpecl input and assumes ac coupling and 100 ? differentialinput termination into the pad (see figure 3). rca j04 o-sstl2 receiver byte clocks: each receiver drives a 106.25 mhz or 53.125 mhz receive byte clock rcn. rcb t03 rcc n12 rcd h14 losa g02 o-sstl2 rx_los, channels a d: receive channel loss of signal. losb m05 if rxnp/n 300mv peak-to-peak differential, losn = logic 0 losc m13 if 150 mv < rxnp/n < 300mv, losn undefined losd g16 if rxnp/n 150 mv peak-to-peak differential, losn = logic 1 rda0 k03 o-sstl2 receive data pins, channel a: parallel data on this bus is valid on the rising and falling edge of rca. see table 2 for rda1 l02 interpretation of this bus under different pmx settings. (see figure 8 for termination) rda2 m01 rda3 k02 rda4 k01 rda5 j02 rda6 h04 rda7 h03 rda8 h02 rda9 h01 rdb0 u04 o-sstl2 receive data pins, channel b: parallel data on this bus is valid on the rising and falling edge of rcb. see table 2 for rdb1 p06 interpretation of this bus under different pmx settings. (see figure 8 for termination) rdb2 t04 rdb3 r04 rdb4 n06 rdb5 p05 rdb6 u02 rdb7 p04 rdb8 t02 rdb9 n04 rdc0 r12 o-sstl2 receive data pins, channel c: parallel data on this bus is valid on the rising and falling edge of rcc. see table 2 for rdc1 u16 interpretation of this bus under different pmx settings. (see figure 8 for termination) rdc2 p12 rdc3 t14 rdc4 t15 rdc5 r14 rdc6 p13 rdc7 p14 rdc8 t16 rdc9 n14
23 rdd0 k15 o-sstl2 receive data pins, channel d: parallel data on this bus is valid on the rising and falling edges of rcd. see tabl e 2 for rdd1 l16 interpretation of this bus under different pmx settings. (see figure 8 for termination) rdd2 m17 rdd3 j14 rdd4 k16 rdd5 k17 rdd6 j16 rdd7 h15 rdd8 h16 rdd9 h17 rxap a01 hs_in received serial data inputs: 0.01 f ac-coupled high-speed differential inputs (see figyre 5). rxan b01 rxbp a03 rxbn b03 rxcp a15 rxcn b15 rxdp a17 rxdn b17 txap a05 hs_ out transmitted serial data outputs: 0.01 f ac-coupled high-speed differential inputs (see figyre 5). note, if high speed txan b05 output driver is disabled, then both outputs are held at logic 1. txbp a07 txbn b07 txcp a11 txcn b11 txdp a13 txdn b13 tca m03 i-sstl2 transmit byte clock: these pins are used to latch transmit data for channels a, b, c, d into the ic. must have the same tcb t07 frequency as reference clock. tcc p10 tcd m15 tdi f04 i-cmos scan test interface: tdi is the test data input, tdo is the test data output, tms is the test mode select, tclk is the test tdo f03 o-cmos clock, and trstn is the test reset pin (active low). tms f02 i-cmos tclk f01 i-cmos trstn g04 i-cmos tda0 p03 i-sstl2 data inputs: parallel data on this bus is clocked in by tca. see timing diagram in figure 9. see table 2 for inte rpretation tda1 r02 of this bus under different pmx settings. tda2 m04 tda3 p02 tda4 l04 tda5 t01 tda6 n02 tda7 k04 tda8 m02 tda9 p01 tdb0 p09 i-sstl2 data inputs: parallel data on this bus is clocked in by tcb. see timing diagram in figure 9. see table 2 for inte rpretation tdb1 u08 of this bus under different pmx settings. tdb2 t08 tdb3 r08 tdb4 p08 tdb5 u06 tdb6 t06 tdb7 t05 tdb8 p07 tdb9 r06 pin list , continued i/o definition name pin type signal
24 tdc0 t09 i-sstl2 data inputs: parallel data on this bus is clocked in by tcc. see timing diagram in figure 9. see table 2 for interpretation tdc1 u10 of this bus under different pmx settings. tdc2 u12 tdc3 t10 tdc4 r10 tdc5 t11 tdc6 t12 tdc7 u14 tdc8 t13 tdc9 p11 tdd0 p15 i-sstl2 data inputs: parallel data on this bus is clocked in by tcd. see timing diagram in figure 9. see table 2 for interpretation tdd1 r16 of this bus under different pmx settings. tdd2 m14 tdd3 p16 tdd4 l14 tdd5 t17 tdd6 n16 tdd7 k14 tdd8 m16 tdd9 p17 vref f13 o-anlg parallel side voltage reference: sstl_2 output reference voltage, vref rrefa d10 o-anlg analog voltage reference: pin used to connect to an external 12k ? (1% or better tolerance) reference resistor, which is connected to ground. rsvn1 d02 i-cmos reserved active low: this is intended for vendor specific functions. tied to v ddq in normal operation. rsvn2 e02 i-cmos reserved active low: this is intended for vendor specific functions. tied to v ddq in normal operation. rsv1 f14 i-cmos reserved active high: this is intended for vendor specific functions. tied to gnd in normal operation. vdd e04, g05, s power supply: normally 1.8 volts. used for core digital logic. g13, j05, j13, l05, l13, m07, m09, m11, n07, n09, n11 vdda1 b02, c01 high speed i/o supply: normally 1.8 volts. used only for the last stage of the high-speed transmitter i/o cells c03, d04 (hs_in/hs_out). due to high current transitions, this supply should be well bypassed to a ground plane. e07 vdda2 a04, a08 a10, a14 vdda1, vdda3: supplies for high-speed differential inputs. b06, b12 c05, c07 vdda2: supply for high-speed differential outputs. c11, c13 d06, d12 e09 vdda3 b16, c15 c17, d14 e11 vddq e0 3 , g01, s digital i/o supply: normally 2.5 volts for sstl_2 i/o pads. g17, j03, j15, l01, l17, n03, n15, r01, r05, r09, r13, r17, u03, u07, u11, u15 pin list , continued i/o definition name pin type signal
25 gndin d01, e14, receiver ground: supply used for input receiver. h13, m06, m12, n08 n10 gndd e01, e17, s dirty ground: supply used by all the n-drivers on the digital pad ring. keeps ground bounce away from the g03, j01, gnd supply. j17, l03, l15, n01 n05, n13 n17, r03 r07, r11 r15, u01 u05, u09 u13, u17 gnd d16, g06, s ground: supply used by the digital portion of the pad ring and by the core. g07, g08, g09, g10, g11, g12, h05, h06, h07, h08, h09, h10, h11, h12, j06, j07, j08, j09, j10, j11, j12, k05, k06, k07, k08, k09, k10, k11, k12, k13, l06, l07, l08, l09, l10, l11, l12, m08, m10 gnda a02, a06 s analog ground: used for tx and rx grounds. a12, a16 b04, b08 b10, b14 c02, c04 c06, c09 c12, c14 c16, d03 d05, d07 d08, d09 d11, d13 d15, e05 e06, e08 e10, e12 e13, f06 f07, f08 f09, f10 f11, f12 pin list , continued i/o definition name pin type signal
26 management interface registers notes: all registers from 0 to 31 not mentioned below are reserved and should not be accessed. ro means read only (any value written will be discarded). rw means the value can be read or written. reserved rw means the value should always be written with the indicated default value. the 2689 responds to four consecutive device addresses, corresponding to the four channels of the device. for example, if the d vad[0:2] input pins are set to 101, then channel a responds to 101 00 , channel b responds to 101 01 , channel c responds to 101 10 , and channel d responds to 101 11 . any information which is not specific to one channel (this includes the information in registers 2, 3, and 19) is obtained and/or s et via channel a (in this example, device address 10100). these registers all contain (common) in their description. accessing the common registers through any channel other than channel a results in undefined behavior and must be avoided. reg 2 phy_id part a (common) default mode 15:0 organization id 16 h0033 ro reg 3 phy_id part b (common) default mode 15:10 organization id 6 h0b ro 9:4 manufacturer s model no. 6 h03 ro 3:0 rev. no. 4 h1 ro registers 2 and 3 are static values that identify the part, and should be read from channel a. they are read-only values. reg 17 speed and configuration default mode 15 transmit full/half speed control (1=full) 1 rw 14 receive full/half speed control (1=full) 1 rw 13 enable comma edge alignment (1: aligned to particular edge, 0: no specific alignment) inverse of pmx pad value rw 12 comma edge alignment (1: positive edge, 0: negative edge) 0 rw 11 enable internal loopback (same function as register 25, bit 13) 0 rw 10 include cdr lock in rx_los 0 rw 9:0 reserved 10 h0 reserved rw the transmit full/half speed control is used to set the transmit path of a channel to either a 2.125 gbd serial rate (when set to logic one) or a 1.0625 gbd serial rate. the receive full/half speed control is used to set the receive path of a channel to either a 2.125 gbd serial rate (when set to logic one) or a 1.0625 gbd serial rate. if rx byte align enable (register 24, bit 1) is set (1), then setting enable comma edge align will caus e the recovered clock output for this channel to be aligned such that the comma characters from an ordered set will be always be clocked on the positive edg e of rcn (when comma edge alignment is 1), or the negative edge of rcn (when comma edge alignment is 0). note that this should only be used if the s pacing of comma containing control codes is appropriate, as for example in fibre channel code sets. the enable loopback bit causes the high spe ed serial data output to be looped back internally to the high speed deserializer if the bit is set to logic one. this causes the data input to the high-s peed input to be ignored. bit 10 causes the rx pll loss of cdr (clock data recovery) lock bit to be included in the losn signal. the default is that losn is det ermined solely by signal amplitude detection on the serial data inputs. reg 19 9 bit error code (common) default mode 15 reserved 0 reserved rw 14:6 nine bit error code[8:0] 9 h1fe rw 5:0 reserved 6 h00 reserved rw register 19 is only applicable in codec mode (pmx=1) and contains the error code output by the 8b/10b decoder when an invalid c ode or disparity error is detected. when this occurs, pins rda[8:0] will contain the nine bit error code, and rda[9] will be asserted to one. on the tran smit side, if an invalid k code is clocked into the tda[9:0] pins, the nine bit error code will be encoded and transmitted. this is a common register: data wri tten to channel a is used for all channels.
27 reg 20 rx loss of signal default mode 15 rx loss of signal (reset to 0) n/a ro 14:0 reserved n/a ro register 20 is the rx loss of signal. it is equivalent to the losn pins, for channels a through d, respectively. reg 22 pvt status register (common) default mode 15:11 reserved 5 b00000 ro 10:6 nen[4:0] 5 b10000 ro 5 reserved 0ro 4:0 pen[4:0] 5 b10000 ro register 22 is used to check the drive strengths for the sstl_2 drivers. reg 23 pvt control register (common) default mode 15:13 reserved 3 b000 reserved rw 12 enable fixed pvt 0 rw 11 reserved 0 reserved rw 10:6 nen[4:0] 5 b00000 rw 5 reserved 0 reserved rw 4:0 pen[4:0] 5 b00000 rw register 23 is used to set the drive strength for the sstl_2 drivers. the pull-up and pull-down drive strengths are set separat ely through pen and nen. for proper operation of terminated sstl_2 drivers, set pen to 5 b11000 and nen to 5 b01000 and set bit 12 to 1 b1. in other words, set register 23 to 16 b0001001000011000 (0x1218). if the reserved bits are not set to zero, unpredictable behavior will occur. reg 24 serdes configuration reg 1 default mode 15:2 reserved 14 h0000 rw 1 rx byte align enable 1 rw 0 serdes channel enable 1 rw register 24 includes writeable configuration of a channel s deserializer. bits 15 through 2 are reserved. bit 1, when set to logic one, causes the channel to byte align to commas, that is, the deserializer will determine the beginning of a 10 bit byte based upon when it recognizes a c omma in the serial data stream. when bit 1 is set to zero, it will randomly determine the beginning of a byte in the serial data stream and will not re align when commas subse- quently arrive in the serial data stream. bit 0 is used to power down both the channel s serializer and deserializer when set to logic 0. when bit 0 is set to logic 0, bit 7 in register 26 must also be set to logic 0 to turn off the associated output driver, minimizing power and ensuri ng the high speed output is not left in an undefined state. management interface registers , continued
reg 25 serdes configuration reg 2 default mode 15 reserved 0 reserved rw 14 pattern error monitor enable 0 rw 13 test loopback enable 0 rw 12 prbs enable 0 rw 11 pattern toggle enable 0 rw 10 user register enable 0 rw 9:0 user register[9:0] 10'h0fa rw register 25 includes writeable configuration for self-test. see the ?est?section under the functional description. reg 26 serdes configuration reg 3 default mode 15:11 tx amplitude[4:0] 5?1f rw 10:8 tx peak[2:0] 3?3 rw 7 tx output driver enable 1 rw 6:0 reserved 7'h00 reserved rw register 26 includes writeable configuration of a channels serializer. bits 15 through 11 and 10 through 8 are used to set the pre-emphasis on the serial output. these values determine the signal amplitude in the bit time immediately after a transition on the high speed output and in subsequent bit times. bit 7, when set to logic one, enable channel to drive the data onto the serial output. when set to logic zero, the serial outputs are pulled high and the data is not driven out. reg 27 serdes status default mode 15:13 reserved 3?000 r0 12 pattern failure detect 1 ro 11 test run complete 0 ro 10:0 reserved 11?000 ro register 27 includes read only status of self test information. see the ?est?section under the functional description. bits 10 through 0 are reserved. management interface registers , continued www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (65) 6756 2394 india, australia, new zealand: (65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (65) 6755 2044 taiwan: (65) 6755 1843 data subject to change. copyright ?2004 agilent technologies, inc. obsoletes 5988-8120en february 2 5 , 2004 5988-9185en

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